Microprocessors (μp) using miniaturized transistors on a semiconductor integrated circuit (IC) may use a state machine or finite state machine (FSM) in the design of their hardware digital system. Microprocessors may also use a programmable state machine.
For example, U.S. Pat. No. 6,799,246 to Wise, et al. discloses a hardware system for receiving data from a memory bus and storing it into a memory array. The memory data can be translated to reside in a different part of the memory array than its associated bus address. This allows flexibility in the storage of the data as well as manipulation of the data by the memory array. A ternary content addressable memory device (TCAM) is used to provide an index of where the data resides from the external memory bus address. A memory hardware assist for memory arrays and data movement with the peripheral bus control signals is disclosed.
Processor systems for system-on-chip (SOC) environments on an Integrated Circuit may use a software based architecture for a generic peripheral processor. However, in practice, the usefulness of this architecture may be limited by protocol requirements of multiple buses. For example, if the protocol of the bus requires responses from a microcontroller (MCU or uController) within a single cycle, the uController may not have the bandwidth to meet the specified response time.
A core IP library is a library of logic designs implementing different functions (e.g.: PCI Core, UART Core, SRAM Core). A core IP library contains a multitude of unique designs that are costly to design, maintain, and migrate from technology to technology nodes. However, the core IP library is needed in the application-specific integrated circuit (ASIC) integrated circuit design function.
Bus adapters between high-speed interfaces are typically implemented using dedicated circuits, for example, within an ASIC. If a flaw is discovered within this dedicated circuit or an interface protocol changes, the ASIC must be redesigned and manufactured at an expense, and significant impact on the length of time it takes for a product to be available for sale (time-to-market).
Peripheral processors or microcontrollers provide the processing necessary to translate one bus standard to another. These processors typically are not the main processors of a system, but are dedicated to handling interface translations. Using these peripheral processors, certain peripheral cores or microcontrollers are replaceable which previously were built with dedicated circuits. Peripheral cores typically use dedicated circuits for performance and size reasons. Bus protocols require state-tracking, and only dedicated circuits could previously handle the performance requirements. However, with technology improvements in the area of performance and size, more general purpose solutions can be reasonably applied.
When using a generic microprocessor to replace a peripheral core, processor, or microcontroller, the variety of protocols which can be supported will depend, among other things, on the performance of the microprocessor. Within a given technology node, this microprocessor can dedicate some maximum number of cycles to analyzing and responding to various states of the peripheral interface. For complex or fast interfaces, this number of cycles may not be sufficient.
It would therefore be desirable to reduce the resulting expense and impact on design, manufacturing and time when an error is found on a dedicated circuit, or when implementing interface protocol changes. It would also be desirable to provide a means for eliminating the need to redesign and manufacture an ASIC when a flaw is discovered, or when implementing interface protocol changes. Further, it would also be desirable for software architecture to provide for controlling multiple protocols on buses.